1. Field of the Invention
The present invention relates to a clock reproduction circuit. In systems for synchronous transmission of digital data, an information signal is transmitted at a constant rate by a transmitting unit, and it is received at the same rate by a receiving unit. Since it is generally impractical to transmit a clock separately from the data, the timing information is usually derived from the data stream itself. Therefore, a circuit for deriving this implicit signal is provided at the receiving unit. In the specification, this circuit is called a clock reproduction circuit, the clock reproduced from the data signal at the receiving unit is called a data clock, and the frequency of the data clock is called a data clock frequency. Further, in recent years, in data communication systems using optical communication equipments and so forth, data is transmitted as a non-return-to-zero (NRZ) signal in order to increase the transmission efficiency. Therefore, the clock reproduction circuit is required to reproduce the clock from the NRZ signal.
2. Description of the Related Art
In the past, a clock reproduction circuit using a high Q value resonator had been used. However, this conventional clock reproduction circuit cannot satisfy the requirement of data communication systems that a clock signal having a wide frequency range be reproduced from a data signal, therefore, a clock reproduction circuit having a Phase Locked Loop (PLL) circuit has been proposed.
In the normal PLL circuit, a phase detector, a loop filter and a voltage controlled oscillator (VCO) are circularly connected. However, if the frequency error between the clock output from the VCO and the data clock is large, the clock from the VCO cannot be made synchronous with the data clock. In the specification, the clock output from the VCO is called a VCO clock, further, the frequency of the VCO clock is called a VCO frequency. Therefore, there is proposed a clock reproduction circuit which includes a phase detector (PD), a quadrature phase detector (QPD) and a frequency detector (PFD) processing the beat notes of the PD and the QPD. The PFD outputs a frequency error signal. Both of the phase error signal output from the PD and the frequency error signal output from the PFD are fed back to the loop filter.
However, the PFD can detect the frequency error only when cycle slips occur and can detect the directions of the cycle slips. Therefore, when the cycle slips do not frequently occur, there occurs a problem that the circuit cannot enter in a locked-in state. To overcome the above drawback, the gains of the PD and the PFD may be raised. In this case, even when the error between the data clock frequency of the data signal and the VCO clock frequency is small, the voltage supplied by the loop filter remains high. However, this technique poses a problem in that the number of timing jitters occurring during data communication increases.
Further, a conventional phase detector (PD) employed in a conventional clock reproduction circuit includes a latch, a one-shot pulse generator and NAND circuits. However, in this conventional PD, when the data signal has a high frequency, it becomes difficult to generate the one-shot pulse. This poses a problem that pulse generation cannot follow the high-frequency data signal.
Further, in a conventional charge pump employed in a conventional reproduction circuit, when the data signal has a high frequency, the one-shot pulse has a shorter pulse duration, the charge pump drive signals have a short pulse duration, and it becomes difficult to respond to these correlative changes. Thus, a high-frequency data signal cannot be handled properly.
Further, in recent years, a semiconductor integrated circuit (IC) in which the error convergence pulse generator, the charge pump, an operational amplifier in the loop filter, and the VCO are incorporated has been realized. When this IC is used, resistors and a capacitor that are included in the loop filter are externally connected to the IC. However, because the output of the charge pump contains a parasitic inductance or capacitance, the parasitic inductance or capacitance is negligible when the data clock frequency is 1 Gbps or higher. This results in a distorted waveform.
Further, because it is difficult to directly synchronize both the frequency and the phase in the clock reproduction circuit with the data clock, another circuit is used in which the frequency of the VCO clock is firstly made to almost agree with that of the reference clock in a first loop, and then the phase of the clock is synchronized with that of the data signal in a second loop. However, because there is an offset between the first and second loops, there occurs a problem that comparatively long time is necessary to synchronize the clock with the data signal after the first loop is switched to the second loop.